Cours:TP printempsM4209 TP 1 Corr

Exercice 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- zero pour allumer les LEDs
entity transcod7segs is
    port (  
            I_in4    : in  std_logic_vector(3 downto 0);
				-- Ordre : gfedcba
            Q_7segs  : out std_logic_vector(6 downto 0)
    );
end transcod7segs;
architecture arch of transcod7segs is begin
  with I_in4 select
    Q_7SEGS <= "1000000" when "0000",
	       "1111001" when "0001",
               "0100100" when "0010",
               "0110000" when "0011",
               "0011001" when X"4",
               "0010010" when X"5",
               "0000010" when X"6",
               "1111000" when X"7",
               "0000000" when X"8",
               "0010000" when X"9",
               "0001000" when X"A",
               "0000011" when X"B",
               "1000110" when X"C",
               "0100001" when X"D",
               "0000110" when X"E",
               "0001110" when others; --X"F"
end arch;

Exercice 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- zero pour allumer les LEDs
entity cmptPassages is
    port (  
            sw    : in  std_logic_vector(7 downto 0);
				-- Ordre : gfedcba
            Diz7segs,Unit7segs  : out std_logic_vector(6 downto 0)
    );
end cmptPassages;
architecture arch_passages of cmptPassages is
component transcod7segs is
    port (  
            I_in4    : in  std_logic_vector(3 downto 0);
				-- Ordre : gfedcba
            Q_7segs  : out std_logic_vector(6 downto 0)
    );
end component transcod7segs;

begin
  unite : transcod7segs port map (
     I_in4 => sw(3 downto 0),
	  Q_7segs => Unit7segs
	  );
  dizaine : transcod7segs port map (
     I_in4 => sw(7 downto 4),
	  Q_7segs => Diz7segs
	  );
end arch_passages;

Le fichier de l'exercice 1 devra absolument faire partie du projet puisqu'il est utilisé dans le fichier ci-dessus.