Cours:Vhdl
Révision datée du 5 novembre 2025 à 10:38 par Bjacquot (discussion | contributions)
Nios 2
interface pour le bus avalon
entity customPeriph is
port (
clk : in std_logic;
reset_n : in std_logic;
address : in std_logic_vector(1 downto 0);
write : in std_logic;
read : in std_logic;
chipselect : in std_logic;
writedata : in std_logic_vector(31 downto 0);
readdata : out std_logic_vector(31 downto 0)
);
end entity customPeriph;