Cours:TP printempsM4209 TP 3 Corr

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Exercice 1

-- description du graphe 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity machine_a_etat is port (
	clk,init : in std_logic;
	g,d : in std_logic;
	en,ud : out std_logic
	);
end machine_a_etat;
	
architecture archi_machine of machine_a_etat is	
	type type_etat is (s1,s2,s3,s4,s5,s6,s7);
	signal next_etat,reg_etat:type_etat;
begin
	valide_etat:process(clk)
   begin
      if rising_edge(clk) then
            if init='1' then
                   reg_etat<=S1;
            else
                   reg_etat<=next_etat;
            end if;
      end if;
   end process valide_etat;
   etat_suivant: process (reg_etat,d,g)
   begin
       --next_etat<=reg_etat;
        case reg_etat is
              when S1=>
                  if d='1' and g='0' then
                          next_etat<=S3;
                  elsif g='1' and d='0' then
                          next_etat<=S2;
                  else
                          next_etat<=S1;
                  end if;
              when S2=>
                  if d='1' then
                         next_etat<=S5;
                  else
                         next_etat<=S2;
                  end if;
             when S3=>
                  if g='1' then
                         next_etat<=S4;
                  else
                         next_etat<=s3;
                  end if;
             when S4=>next_etat<=S6;

             when S5=>next_etat<=S7;

             when S6=>
                  if g='0' then
                         next_etat<=S1;
                  else
                         next_etat<=S6;
                  end if;
             when S7=>
                  if d='0' then
                         next_etat<=S1;
                  else
                         next_etat<=S7;
                  end if;
             end case;
	end process etat_suivant;
-- gestion des actions
   ud <= '1' when reg_etat = S3 else
	      '1' when reg_etat = S4 else
			'1' when reg_etat = S6 else
			'0';
	en <= '1' when reg_etat = S4 else
	      '1' when reg_etat = S5 else
	      '0';
end archi_machine;