Cours:TP printempsM4209 TP 5 Corr : Différence entre versions

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<accesscontrol>Acces:Prof</accesscontrol>
 +
==Partie matérielle==
 +
<source lang=VHDL>
 +
----------------------------------------------------------------------------------
 +
-- Company:
 +
-- Engineer:
 +
--
 +
-- Create Date:    08:57:48 08/26/2014
 +
-- Design Name:
 +
-- Module Name:    microcontroleur - microcontroleur_architecture
 +
-- Project Name:
 +
-- Target Devices:
 +
-- Tool versions:
 +
-- Description:
 +
--
 +
-- Dependencies:
 +
--
 +
-- Revision:
 +
-- Revision 0.01 - File Created
 +
-- Additional Comments:
 +
--
 +
----------------------------------------------------------------------------------
 +
library IEEE;
 +
use IEEE.STD_LOGIC_1164.ALL;
 +
use IEEE.STD_LOGIC_ARITH.ALL;
 +
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 +
 +
---- Uncomment the following library declaration if instantiating
 +
---- any Xilinx primitives in this code.
 +
--library UNISIM;
 +
--use UNISIM.VComponents.all;
 +
 +
entity Tiny861 is
 +
    Port ( clk : in  STD_LOGIC;
 +
          Rst : in  STD_LOGIC;
 +
  sw : in STD_LOGIC_VECTOR (7 downto 0);
 +
  In_PINB : in STD_LOGIC_VECTOR (7 downto 0);
 +
          Led : out  STD_LOGIC_VECTOR (7 downto 0);
 +
  Diz7segs : out  STD_LOGIC_VECTOR (7 downto 0);
 +
  Aff7segs : out  STD_LOGIC_VECTOR (7 downto 0));
 +
end Tiny861;
 +
 +
architecture microcontroleur_architecture of Tiny861 is
 +
--Registres et PORTs de l'ATTiny861
 +
constant OCR1A : std_logic_vector(5 downto 0) := "101101";
 +
constant OCR1B : std_logic_vector(5 downto 0) := "101100";
 +
constant PORTA : std_logic_vector(5 downto 0) := "011011";
 +
constant DDRA : std_logic_vector(5 downto 0) := "011010";
 +
constant PINA : std_logic_vector(5 downto 0) := "011001";
 +
constant PORTB : std_logic_vector(5 downto 0) := "011000";
 +
constant DDRB : std_logic_vector(5 downto 0) := "010111";
 +
constant PINB : std_logic_vector(5 downto 0) := "010110";
 +
constant ADCH : std_logic_vector(5 downto 0) := "000101";
 +
constant ADCL : std_logic_vector(5 downto 0) := "000100";
 +
--Registres non présents dans l'ATTiny861
 +
constant UDR : std_logic_vector(5 downto 0) := "000011";
 +
constant UCSRA : std_logic_vector(5 downto 0) := "000010";
 +
constant UCSRB : std_logic_vector(5 downto 0) := "000001";
 +
component mcu_core is
 +
Port (
 +
Clk : in std_logic;
 +
Rst : in std_logic; -- Reset core when Rst='1'
 +
En : in std_logic; -- CPU stops when En='0', could be used to slow down cpu to save power
 +
-- PM
 +
PM_A : out std_logic_vector(15 downto 0);
 +
PM_Drd : in std_logic_vector(15 downto 0);
 +
-- DM
 +
DM_A : out std_logic_vector(15 downto 0); -- 0x00 - xxxx
 +
DM_Areal : out std_logic_vector(15 downto 0); -- 0x60 - xxxx (same as above + io-adr offset)
 +
DM_Drd : in std_logic_vector(7 downto 0);
 +
DM_Dwr : out std_logic_vector(7 downto 0);
 +
DM_rd : out std_logic;
 +
DM_wr : out std_logic;
 +
-- IO
 +
IO_A : out std_logic_vector(5 downto 0); -- 0x00 - 0x3F
 +
IO_Drd : in std_logic_vector(7 downto 0);
 +
IO_Dwr : out std_logic_vector(7 downto 0);
 +
IO_rd : out std_logic;
 +
IO_wr : out std_logic;
 +
-- OTHER
 +
  OT_FeatErr : out std_logic; -- Feature error! (Unhandled part of instruction)
 +
  OT_InstrErr : out std_logic -- Instruction error! (Unknown instruction)
 +
);
 +
end component mcu_core;
 +
--PM
 +
component pm  is
 +
Port (
 +
Clk : in std_logic;
 +
rst : in std_logic; -- Reset when Rst='1'
 +
-- PM
 +
PM_A : in std_logic_vector(15 downto 0);
 +
PM_Drd : out std_logic_vector(15 downto 0)
 +
);
 +
end component pm;
 +
 +
  component dm is
 +
    Port ( clk : in  STD_LOGIC;
 +
          addr : in  STD_LOGIC_VECTOR (15 downto 0);
 +
          dataread : out  STD_LOGIC_VECTOR (7 downto 0);
 +
          datawrite : in  STD_LOGIC_VECTOR (7 downto 0);
 +
          rd : in  STD_LOGIC;
 +
          wr : in  STD_LOGIC);
 +
  end component dm;
 +
 +
  component transcod7segs is
 +
    port ( 
 +
            I_in4    : in  std_logic_vector(3 downto 0);
 +
-- Ordre : gfedcba
 +
            Q_7segs  : out std_logic_vector(6 downto 0)
 +
    );
 +
end component transcod7segs;
 +
 +
signal PM_A : std_logic_vector(15 downto 0);
 +
signal PM_Drd : std_logic_vector(15 downto 0);
 +
-- DM
 +
signal DM_A : std_logic_vector(15 downto 0); -- 0x00 - xxxx
 +
signal DM_Areal : std_logic_vector(15 downto 0); -- 0x60 - xxxx (same as above + io-adr offset)
 +
signal DM_Drd : std_logic_vector(7 downto 0);
 +
signal DM_Dwr : std_logic_vector(7 downto 0);
 +
signal DM_rd : std_logic;
 +
signal DM_wr : std_logic;
 +
-- IO
 +
signal IO_A : std_logic_vector(5 downto 0); -- 0x00 - 0x3F
 +
signal IO_Drd : std_logic_vector(7 downto 0);
 +
signal IO_Dwr : std_logic_vector(7 downto 0);
 +
signal IO_rd : std_logic;
 +
signal IO_wr : std_logic;
 +
 +
signal IO_DrdA : std_logic_vector(7 downto 0);
 +
signal IO_DrdB : std_logic_vector(7 downto 0);
 +
  signal s_PORTB : std_logic_vector(7 downto 0);
 +
begin
 +
 +
core : mcu_core Port map (
 +
Clk => clk,
 +
Rst => Rst,
 +
En => '1',
 +
-- PM
 +
PM_A => PM_A,
 +
PM_Drd => PM_Drd,
 +
-- DM
 +
DM_A => DM_A,
 +
DM_Areal => DM_Areal,
 +
DM_Drd => DM_Drd,
 +
DM_Dwr => DM_Dwr,
 +
DM_rd => DM_rd,
 +
DM_wr => DM_wr,
 +
-- IO
 +
IO_A => IO_A,
 +
IO_Drd => IO_Drd,
 +
IO_Dwr => IO_Dwr,
 +
IO_rd => IO_rd,
 +
IO_wr => IO_wr,
 +
-- OTHER
 +
OT_FeatErr => open,
 +
OT_InstrErr => open
 +
);
 +
 +
prgmem : pm port map (
 +
Clk => clk,
 +
Rst => '0',
 +
-- PM
 +
PM_A => PM_A,
 +
PM_Drd => PM_Drd
 +
);
 +
 +
datamem : dm port map (
 +
          clk => clk,
 +
          addr => DM_A,
 +
          dataread  => DM_Drd,
 +
          datawrite => DM_Dwr,
 +
          rd => DM_rd,
 +
          wr => DM_wr
 +
);
 +
 +
transcodage_unite: transcod7segs port map ( 
 +
            I_in4 =>  s_PORTB(3 downto 0),
 +
-- Ordre : gfedcba
 +
            Q_7segs  => Aff7segs(6 downto 0)
 +
        );
 +
 +
transcodage_dizaine: transcod7segs port map ( 
 +
            I_in4 =>  s_PORTB(7 downto 4),
 +
-- Ordre : gfedcba
 +
            Q_7segs  => Diz7segs(6 downto 0)
 +
        );
 +
 +
-- IO write process
 +
--
 +
    iowr: process(CLK)
 +
    begin
 +
        if (rising_edge(CLK)) then
 +
            if (IO_wr = '1') then
 +
                case IO_A is
 +
-- addresses for tiny861 device (use io.h).
 +
      --
 +
                    when PORTA  => -- PORTA=X"1B" (0X3B)
 +
                                  Led <= IO_Dwr;
 +
    when  PORTB => -- PORTB=X"18" (0X38)
 +
          s_PORTB <= IO_Dwr;
 +
--                  when  DDRB => -- PORTB=X"17" (0X37)
 +
--         Diz7segs <= IO_Dwr;  
 +
                    when others =>
 +
                end case;
 +
            end if;
 +
        end if;
 +
    end process;
 +
 +
-- IO read process
 +
--
 +
    iord: process(IO_rd,IO_A,In_PINB,sw)
 +
    begin
 +
        -- addresses for tinyX6 device (use iom8.h).
 +
        --
 +
      if IO_rd = '1' then
 +
          case IO_A is
 +
            when  PINA => IO_Drd <= sw;  -- PINA=X"19" (0X39)
 +
            when  PINB => IO_Drd <= In_PINB;  -- PINB=X"16" (0X36)
 +
            when others => IO_Drd <= X"AA";
 +
          end case;
 +
      end if;
 +
    end process;
 +
 +
end microcontroleur_architecture;
 +
 +
</source>
 +
==Programme c==
 
<source lang=c>
 
<source lang=c>
 
#include "avr/io.h"
 
#include "avr/io.h"

Version du 9 mars 2016 à 17:47

Il s’agit d’une page protégée.

Partie matérielle

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:57:48 08/26/2014 
-- Design Name: 
-- Module Name:    microcontroleur - microcontroleur_architecture 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Tiny861 is
    Port ( clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
			  sw : in STD_LOGIC_VECTOR (7 downto 0);
			  In_PINB : in STD_LOGIC_VECTOR (7 downto 0);
           Led : out  STD_LOGIC_VECTOR (7 downto 0);
			  Diz7segs : out  STD_LOGIC_VECTOR (7 downto 0);
			  Aff7segs : out  STD_LOGIC_VECTOR (7 downto 0));
end Tiny861;

architecture microcontroleur_architecture of Tiny861 is
--Registres et PORTs de l'ATTiny861
constant OCR1A : std_logic_vector(5 downto 0) := "101101";
constant OCR1B : std_logic_vector(5 downto 0) := "101100";
constant PORTA : std_logic_vector(5 downto 0) := "011011";
constant DDRA : std_logic_vector(5 downto 0) := "011010";
constant PINA : std_logic_vector(5 downto 0) := "011001";
constant PORTB : std_logic_vector(5 downto 0) := "011000";
constant DDRB : std_logic_vector(5 downto 0) := "010111";
constant PINB : std_logic_vector(5 downto 0) := "010110";
constant ADCH : std_logic_vector(5 downto 0) := "000101";
constant ADCL : std_logic_vector(5 downto 0) := "000100";
--Registres non présents dans l'ATTiny861
constant UDR : std_logic_vector(5 downto 0) := "000011";
constant UCSRA : std_logic_vector(5 downto 0) := "000010";
constant UCSRB : std_logic_vector(5 downto 0) := "000001";
	component mcu_core is
		Port (
			Clk	: in std_logic;
			Rst	: in std_logic; -- Reset core when Rst='1'
			En		: in std_logic; -- CPU stops when En='0', could be used to slow down cpu to save power
			-- PM
			PM_A		: out std_logic_vector(15 downto 0);
			PM_Drd	: in std_logic_vector(15 downto 0);
			-- DM
			DM_A		: out std_logic_vector(15 downto 0); -- 0x00 - xxxx
			DM_Areal	: out std_logic_vector(15 downto 0); -- 0x60 - xxxx (same as above + io-adr offset)
			DM_Drd	: in std_logic_vector(7 downto 0);
			DM_Dwr	: out std_logic_vector(7 downto 0);
			DM_rd		: out std_logic;
			DM_wr		: out std_logic;
			-- IO
			IO_A		: out std_logic_vector(5 downto 0); -- 0x00 - 0x3F
			IO_Drd	: in std_logic_vector(7 downto 0);
			IO_Dwr	: out std_logic_vector(7 downto 0);
			IO_rd		: out std_logic;
			IO_wr		: out std_logic;
			-- OTHER
		   OT_FeatErr	: out std_logic; -- Feature error! (Unhandled part of instruction)
		   OT_InstrErr	: out std_logic -- Instruction error! (Unknown instruction)
		);
	end component mcu_core;
	--PM
	component pm  is
		Port (
				Clk	: in std_logic;
				rst	: in std_logic; -- Reset when Rst='1'
				-- PM
				PM_A		: in std_logic_vector(15 downto 0);
				PM_Drd	: out std_logic_vector(15 downto 0)
		);
	end component pm;	

  component dm is
    Port ( clk : in  STD_LOGIC;
           addr : in  STD_LOGIC_VECTOR (15 downto 0);
           dataread : out  STD_LOGIC_VECTOR (7 downto 0);
           datawrite : in  STD_LOGIC_VECTOR (7 downto 0);
           rd : in  STD_LOGIC;
           wr : in  STD_LOGIC);
  end component dm;

  component transcod7segs is
    port (  
            I_in4    : in  std_logic_vector(3 downto 0);
				-- Ordre : gfedcba
            Q_7segs  : out std_logic_vector(6 downto 0)
    );
end component transcod7segs;

	signal PM_A		: std_logic_vector(15 downto 0);
	signal PM_Drd	: std_logic_vector(15 downto 0);
	-- DM
	signal DM_A			: std_logic_vector(15 downto 0); -- 0x00 - xxxx
	signal DM_Areal	: std_logic_vector(15 downto 0); -- 0x60 - xxxx (same as above + io-adr offset)
	signal DM_Drd		: std_logic_vector(7 downto 0);
	signal DM_Dwr		: std_logic_vector(7 downto 0);
	signal DM_rd		: std_logic;
	signal DM_wr		: std_logic;
	-- IO
	signal IO_A		: std_logic_vector(5 downto 0); -- 0x00 - 0x3F
	signal IO_Drd	: std_logic_vector(7 downto 0);
	signal IO_Dwr	: std_logic_vector(7 downto 0);
	signal IO_rd	: std_logic;
	signal IO_wr	: std_logic;

	signal IO_DrdA	: std_logic_vector(7 downto 0);
	signal IO_DrdB	: std_logic_vector(7 downto 0);
   signal s_PORTB	: std_logic_vector(7 downto 0);
begin

	core : mcu_core Port map (
		Clk	=> clk,
		Rst	=> Rst,
		En		=> '1',
		-- PM
		PM_A		=> PM_A,
		PM_Drd	=> PM_Drd,
		-- DM
		DM_A		=> DM_A,
		DM_Areal	=> DM_Areal,
		DM_Drd	=> DM_Drd,
		DM_Dwr	=> DM_Dwr,
		DM_rd		=> DM_rd,
		DM_wr		=> DM_wr,
		-- IO
		IO_A		=> IO_A,
		IO_Drd	=> IO_Drd,
		IO_Dwr	=> IO_Dwr,
		IO_rd		=> IO_rd,
		IO_wr		=> IO_wr,
		-- OTHER
		OT_FeatErr => open,
		OT_InstrErr	=> open
	);

	prgmem : pm port map (
			Clk	=> clk,
			Rst	=> '0',
			-- PM
			PM_A		=> PM_A,
			PM_Drd	=> PM_Drd
	);
	
	datamem : dm port map (
           clk => clk,
           addr => DM_A,
           dataread  => DM_Drd,
           datawrite => DM_Dwr,
           rd => DM_rd, 
           wr =>	DM_wr
	);
	
	transcodage_unite: transcod7segs port map (  
            I_in4 =>  s_PORTB(3 downto 0),
			-- Ordre : gfedcba
            Q_7segs  => Aff7segs(6 downto 0)
         );
	 
	transcodage_dizaine: transcod7segs port map (  
            I_in4 =>  s_PORTB(7 downto 4),
		-- Ordre : gfedcba
            Q_7segs  => Diz7segs(6 downto 0)
         );
	
	-- IO write process
--
    iowr: process(CLK)
    begin
        if (rising_edge(CLK)) then
            if (IO_wr = '1') then
                case IO_A is
		 -- addresses for tiny861 device (use io.h).
       --
                    when PORTA  => -- PORTA=X"1B" (0X3B)
                                   Led <= IO_Dwr;
		    when  PORTB => -- PORTB=X"18" (0X38)
			           s_PORTB <= IO_Dwr;
--                  when  DDRB => -- PORTB=X"17" (0X37)
--			        Diz7segs <= IO_Dwr;												  
                    when others =>
                end case;
            end if;
        end if;
    end process;
	 
-- IO read process
--
    iord: process(IO_rd,IO_A,In_PINB,sw)
    begin
        -- addresses for tinyX6 device (use iom8.h).
        --
      if IO_rd = '1' then
          case IO_A is
            when  PINA => IO_Drd <= sw;  -- PINA=X"19" (0X39)
            when  PINB => IO_Drd <= In_PINB;  -- PINB=X"16" (0X36)
            when others => IO_Drd <= X"AA";
          end case;
      end if;
    end process;

end microcontroleur_architecture;

Programme c

#include "avr/io.h"
#undef F_CPU 
#define F_CPU 15000000UL
#include "util/delay.h"

//#define UCSRB	_SFR_IO8(0x01) 
//#define UCSRA	_SFR_IO8(0x02) 
//#define UDR	_SFR_IO8(0x03)
// UCSRA
//#define RXC 7
//#define TXC 6
//#define UDRE 5
//UCSRB
//#define RXEN 4
//#define TXEN 3

//const unsigned char digit7segs[16]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90,0x88,0x83,0xC6,0xA1,0x86,0x8E}; 
void incrementBCD(unsigned char *cnt);
void decrementBCD(unsigned char *cnt);
//***********************************************************************
// main 
//*********************************************************************** 

 int main (void) {
   //unsigned char transcod7segs[]={0xFE,0xFD,0xFB,0xF7,0xEF,0xDF,0xBF,0xFF,0x00};
   //unsigned char transcod7segs[]={0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0x10};

   unsigned char cmpt=0,ch=128,swPresent=0,swPasse=0,etat=1; 
   while(1) { 
   // compteur simple
   //  PORTB = transcod7segs[cmpt&0x0F];
   //  DDRB = transcod7segs[(cmpt&0xF0)>>4];
     PORTB= cmpt; 
     swPresent = PINA;
     switch (etat) {
        case 0x01 : if (((swPresent & 0x03)==0x01) && ((swPasse & 0x01)==0x00)) {etat = 0x02;break;}
                    if (((swPresent & 0x03)==0x02) && ((swPasse & 0x02)==0x00)) {etat = 0x08;break;}    
        case 0x02 : if (((swPresent & 0x03)==0x02) && ((swPasse & 0x02)==0x00)) etat = 0x04;break;
        case 0x04 : etat = 0x01; break;        
        case 0x08 : if (((swPresent & 0x03)==0x01) && ((swPasse & 0x01)==0x00)) etat = 0x10;break;
        case 0x10 : etat = 0x01; break;
        default : etat = 0x01;
      }
      if (etat==0x04) incrementBCD(&cmpt);
      if (etat==0x10) decrementBCD(&cmpt);
      swPasse = swPresent;
     PORTA = ch;
     ch >>= 1; 
     if (ch == 0) ch = 128;
     _delay_ms(300); // on verra passer les caractères     
   } 
   return 0; 
 }

void incrementBCD(unsigned char *cnt) { 
  (*cnt)++;    
  if ((*cnt & 0x0F) > 0x09) *cnt += 6; 
  if ((*cnt & 0xF0) > 0x90) *cnt = 0; 
} 

void decrementBCD(unsigned char *cnt) { 
  (*cnt)--;    
  if ((*cnt & 0x0F) == 0x0F) *cnt -= 6; 
  if ((*cnt & 0xF0) == 0xF0) *cnt = 0x99; 
}
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