Cours:TP printempsM4209 TP 2 Corr

Exercice 1

-- description du composant compteur/decompteur cascadable
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity compteurbcd is port (
		clk :in std_logic;
		en : in std_logic;
		init : in std_logic;
--ud=1 up, ud=0 down
		ud : in std_logic;
		enout : out std_logic;
		s: out std_logic_vector(3 downto 0)
		);
end entity;
	
architecture behavior of compteurbcd is
	signal n : std_logic_vector(3 downto 0);
	begin
	increment : process(clk) begin
          if clk'event and clk='1' then
            if init ='1' then
              n <= (others => '0');
            elsif en='1' then
              if ud = '1' then  --up
                if n<9 then
                  n <= n + 1 ;
                else
                  n <= (others => '0');
                end if;
              else -- down
                if n>0 then 
                   n <= n - 1;
                else
                   n <= "1001";
                end if;
              end if;
            end if;	
          end if;
	end process;
-- gestion enout
   enout <= '1' when en='1' and ud='1' and n=9 else
	    '1' when en='1' and ud='0' and n=0 else
            '0';
   s <= n;
end behavior;

Exercice 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- zero pour allumer les LEDs
entity cmptPassages is
    port (  
            downUp, en, Init, clk    : in  std_logic;
				-- Ordre : gfedcba
            Diz7segs,Unit7segs  : out std_logic_vector(6 downto 0)
    );
end cmptPassages;

architecture arch_passages of cmptPassages is
component transcod7segs is
    port (  
            I_in4    : in  std_logic_vector(3 downto 0);
				-- Ordre : gfedcba
            Q_7segs  : out std_logic_vector(6 downto 0)
    );
end component transcod7segs;

component compteurbcd is port (
		clk :in std_logic;
		en : in std_logic;
		init : in std_logic;
--ud=1 up, ud=0 down
		ud : in std_logic;
		enout : out std_logic;
		s: out std_logic_vector(3 downto 0)
		);
end component;

component lent is port (
  clk : in std_logic;
  h_lente : out std_logic
  );
end component;

signal s_unite, s_diz : std_logic_vector(3 downto 0);
signal s_clk, s_en : std_logic;

begin
  horl_lente:lent port map(
    clk => clk,
	 h_lente => s_clk
  );
  
  cmpt_unite : compteurbcd port map(
    clk => s_clk,
	 en => en,
	 init => init,
	 ud => downUp,
	 enout => s_en,
	 s => s_unite
	 );
	 cmpt_diz : compteurbcd port map(
    clk => s_clk,
	 en => s_en,
	 init => init,
	 ud => downUp,
	 enout => open,
	 s => s_diz
	 );
  unite : transcod7segs port map (
     I_in4 => s_unite,
	  Q_7segs => Unit7segs
	  );
  dizaine : transcod7segs port map (
     I_in4 => s_diz,
	  Q_7segs => Diz7segs
	  );
end arch_passages;

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity lent is port (
  clk : in std_logic;
  h_lente : out std_logic
  );
end lent;

architecture arch_lent of lent is
signal cmpt : std_logic_vector(23 downto 0);
begin
  process(clk) begin
    if rising_edge(clk) then
	   cmpt <= cmpt + 1;
    end if;
  end process;
  h_lente <= cmpt(23);
end arch_lent;

Évidemment les fichiers du transcodeur (TP1 exo1) et du compteur BCD (exo 1 de ce TP2) sont à ajouter au projet.