Cours:TP printempsM4209 TP 3 Corr

Exercice 1

-- description du graphe 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity machine_a_etat is port (
	clk,init : in std_logic;
	g,d : in std_logic;
	en,ud : out std_logic
	);
end machine_a_etat;
	
architecture archi_machine of machine_a_etat is	
	type type_etat is (s1,s2,s3,s4,s5,s6,s7);
	signal next_etat,reg_etat:type_etat;
begin
	valide_etat:process(clk)
   begin
      if rising_edge(clk) then
            if init='1' then
                   reg_etat<=S1;
            else
                   reg_etat<=next_etat;
            end if;
      end if;
   end process valide_etat;
   etat_suivant: process (reg_etat,d,g)
   begin
       --next_etat<=reg_etat;
        case reg_etat is
              when S1=>
                  if d='1' and g='0' then
                          next_etat<=S3;
                  elsif g='1' and d='0' then
                          next_etat<=S2;
                  else
                          next_etat<=S1;
                  end if;
              when S2=>
                  if d='1' then
                         next_etat<=S5;
                  else
                         next_etat<=S2;
                  end if;
             when S3=>
                  if g='1' then
                         next_etat<=S4;
                  else
                         next_etat<=s3;
                  end if;
             when S4=>next_etat<=S6;

             when S5=>next_etat<=S7;

             when S6=>
                  if g='0' then
                         next_etat<=S1;
                  else
                         next_etat<=S6;
                  end if;
             when S7=>
                  if d='0' then
                         next_etat<=S1;
                  else
                         next_etat<=S7;
                  end if;
             end case;
	end process etat_suivant;
-- gestion des actions
   ud <= '1' when reg_etat = S3 else
	      '1' when reg_etat = S4 else
			'1' when reg_etat = S6 else
			'0';
	en <= '1' when reg_etat = S4 else
	      '1' when reg_etat = S5 else
	      '0';
end archi_machine;

et l'ensemble complet :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- zero pour allumer les LEDs
entity cmptPassages is
    port (  
            capteurGauche,capteurDroit, Rst, clk    : in  std_logic;
				-- Ordre : gfedcba
            Diz7segs,Unit7segs  : out std_logic_vector(6 downto 0)
    );
end cmptPassages;

architecture arch_passages of cmptPassages is
component transcod7segs is
    port (  
            I_in4    : in  std_logic_vector(3 downto 0);
				-- Ordre : gfedcba
            Q_7segs  : out std_logic_vector(6 downto 0)
    );
end component transcod7segs;

component compteurbcd is port (
		clk :in std_logic;
		en : in std_logic;
		init : in std_logic;
--ud=1 up, ud=0 down
		ud : in std_logic;
		enout : out std_logic;
		s: out std_logic_vector(3 downto 0)
		);
end component;

component lent is port (
  clk : in std_logic;
  h_lente : out std_logic
  );
end component;

component machine_a_etat is port (
	clk,init : in std_logic;
	g,d : in std_logic;
	en,ud : out std_logic
);
end component;

signal s_unite, s_diz : std_logic_vector(3 downto 0);
signal s_clk, s_en,ss_en,s_ud : std_logic;

begin
  horl_lente:lent port map(
    clk => clk,
	 h_lente => s_clk
  );
  
  sequenceur:machine_a_etat port map(
    clk => s_clk,
	 init => Rst,
	 g => capteurGauche,
	 d => capteurDroit,
	 en => ss_en,
	 ud => s_ud
	 );
  
  cmpt_unite : compteurbcd port map(
    clk => s_clk,
	 en => ss_en,
	 init => Rst,
	 ud => s_ud,
	 enout => s_en,
	 s => s_unite
	 );
	 cmpt_diz : compteurbcd port map(
    clk => s_clk,
	 en => s_en,
	 init => Rst,
	 ud => s_ud,
	 enout => open,
	 s => s_diz
	 );
  unite : transcod7segs port map (
     I_in4 => s_unite,
	  Q_7segs => Unit7segs
	  );
  dizaine : transcod7segs port map (
     I_in4 => s_diz,
	  Q_7segs => Diz7segs
	  );
end arch_passages;

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity lent is port (
  clk : in std_logic;
  h_lente : out std_logic
  );
end lent;

architecture arch_lent of lent is
signal cmpt : std_logic_vector(23 downto 0);
begin
  process(clk) begin
    if rising_edge(clk) then
	   cmpt <= cmpt + 1;
    end if;
  end process;
  h_lente <= cmpt(23);
end arch_lent;