Cours:TP M1102 TP 6 Corr

TP6

Exercice 1 : le réveil

Il n'y a pas grand chose à dire sur la correction à part que l'on n'utilise pas l'horloge 50 MHz directement mais le 3Hz que l'on sait fabriquer depuis le tp 3.

-- Vérifié OK le 29/09/20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY tp6 IS PORT (
  clk, key, trip : IN std_logic;
  Led0: OUT std_logic);
END tp6;

ARCHITECTURE arch_tp6 OF tp6 IS
-- les composants :
COMPONENT SequSonnerie IS
  PORT(                  
        clock,Key,Trip,ena :IN std_logic;
        Ring :OUT std_logic
        );
END COMPONENT SequSonnerie;

COMPONENT cmpt24bits IS
  PORT(clk_50MHz : IN STD_LOGIC; -- une seule entrée
    clk_slow : OUT STD_LOGIC); -- une seule sortie
END COMPONENT cmpt24bits;
-- LE FIL INTENE
SIGNAL s_horloge_lente : std_logic;
BEGIN
  i1 : cmpt24bits PORT MAP(
      clk_50MHz => clk,
      clk_slow => s_horloge_lente);
	 
  i2 : SequSonnerie PORT MAP (
         clock => s_horloge_lente,
			Key => Key,
			Trip => Trip,
			ena => '1',
         Ring => led0);
END arch_tp6;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY SequSonnerie IS
  PORT(                  
        clock,Key,Trip,ena :IN std_logic;
        Ring :OUT std_logic
        );
END SequSonnerie;

ARCHITECTURE arch_SequSonnerie  OF SequSonnerie IS
  TYPE typetat IS (Armed, Off, Ringing); 
  SIGNAL etatp, etatf : typetat;
  BEGIN
-- partie séquentielle
    PROCESS (clock) BEGIN  -- 1er process
	 IF Clock ='1' AND Clock'EVENT THEN
	   IF ena = '1' then
            etatp <= etatf;
		END IF;
     END IF;
    END PROCESS;
    PROCESS(etatp) BEGIN --2eme process
        CASE etatp IS
             WHEN Off => IF key ='1' THEN etatf <= Armed; 
                         ELSE etatf <= Off;
                      END IF;  
             WHEN Armed => IF Key = '0' THEN 
                            etatf <= Off;
	                   ELSIF Trip ='1' THEN 
                             etatf <= Ringing;
	                   ELSE etatf <= Armed;
	                  END IF; 
             WHEN Ringing => IF Key ='0' THEN 
                                 etatf <= Off; 
                            ELSE etatf <= Ringing;
			    END IF; 
	        END CASE;
    END PROCESS;
-- partie combinatoire
   Ring <= '1' WHEN etatp=Ringing ELSE
           '0';
END arch_SequSonnerie;

-- horloge lente 3 Hz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY cmpt24bits IS
  PORT(clk_50MHz : IN STD_LOGIC; -- une seule entrée
    clk_slow : OUT STD_LOGIC); -- une seule sortie
END cmpt24bits;
 
ARCHITECTURE arch_cmpt24bits OF cmpt24bits IS
  signal cmpt : std_logic_vector(23 downto 0);
BEGIN
  process(clk_50MHz) begin
    if rising_edge(clk_50MHz) then
      cmpt <= cmpt + 1;
    end if;
  end process;
  clk_slow <= cmpt(23);  -- partie combinatoire de construction de l'horloge lente
END arch_cmpt24bits;

Voici le fichier de contraintes associé :

To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation

clk,Input,PIN_P11,,,,3.3-V LVTTL,,,,,

Key,Unknown,PIN_C10,7,B7_N0,PIN_C10,3.3-V LVTTL,,,,,
Trip,Unknown,PIN_C11,7,B7_N0,PIN_C11,3.3-V LVTTL,,,,,

LED0,Unknown,PIN_A8,7,B7_N0,PIN_A8,3.3-V LVTTL,,,,,