Cours:TP M1102 TP 4 Corr

TP 4

Exercice 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY cmpt24bits IS
  PORT(clk_50MHz : IN STD_LOGIC; -- une seule entrée
    clk_slow : OUT STD_LOGIC); -- une seule sortie
END cmpt24bits;
 
ARCHITECTURE arch_cmpt24bits OF cmpt24bits IS
  signal cmpt : std_logic_vector(23 downto 0);
BEGIN
  process(clk_50MHz) begin
    if rising_edge(clk_50MHz) then
      cmpt <= cmpt + 1;
    end if;
  end process;
  clk_slow <= cmpt(23);  -- partie combinatoire de construction de l'horloge lente
END arch_cmpt24bits;

Exercice 3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY cmpt7seg IS
  PORT(CLK : IN STD_LOGIC;
    s_7segs : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END cmpt7seg;
ARCHITECTURE arch OF cmpt7seg IS -- comment éviter les equations
  SIGNAL s7segs : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
  PROCESS(clk) BEGIN
    IF (clk'EVENT AND clk='1') THEN
     CASE s7segs is --style case when
       WHEN "1000000" => s7segs <="1111001"; -- premiere transition 
       WHEN "1111001" => s7segs <="0100100"; -- deuxieme transition
       WHEN "0100100" => s7segs <="0110000"; -- troisieme transition
       WHEN "0110000" => s7segs <="0011001";
       WHEN "0011001" => s7segs <="0010010";
       WHEN "0010010" => s7segs <="0000010";
       WHEN "0000010" => s7segs <="1111000";
       WHEN "1111000" => s7segs <="0000000";
       WHEN "0000000" => s7segs <="0010000";
       WHEN "0010000" => s7segs <="1000000"; -- dernière transition
-- dans tous les autres cas on revient sur 8 ce qui utilise 42 LE contre 45 LE pour bouclage à 0 !!!!
       WHEN OTHERS => s7segs <="0000000"; 
     END CASE;
   END IF;
  END PROCESS;
  s_7segs <=s7segs;
END arch;