Cours:TP M1102 TP 2 Corr : Différence entre versions
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+ | |||
+ | Et voici le programme de correction : | ||
+ | |||
+ | <source lang=vhdl> | ||
+ | library IEEE; | ||
+ | use IEEE.STD_LOGIC_1164.ALL; | ||
+ | ENTITY transcod7segs IS PORT( | ||
+ | sw : in std_logic_vector(3 downto 0); | ||
+ | s7segs : out std_logic_vector(6 downto 0)); | ||
+ | END transcod7segs; | ||
+ | ARCHITECTURE arch of transcod7segs IS | ||
+ | BEGIN | ||
+ | with sw select | ||
+ | --gfedcba | ||
+ | s7segs <= "1000000" when "0000", | ||
+ | "1111001" when "0001", | ||
+ | "0100100" when "0010", | ||
+ | "0110000" when "0011", | ||
+ | "0011001" when "0100", | ||
+ | "0010010" when "0101", | ||
+ | "0000010" when "0110", | ||
+ | "1111000" when "0111", | ||
+ | "0000000" when "1000", | ||
+ | "0010000" when "1001", | ||
+ | "0001000" when "1010", | ||
+ | "0000011" when "1011", | ||
+ | "1000110" when "1100", | ||
+ | "0100001" when "1101", | ||
+ | "0000110" when "1110", | ||
+ | "0001110" when others; | ||
+ | END; | ||
+ | </source> |
Version du 23 septembre 2020 à 18:55
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TP2
Exercice 1 : Multiplieur de deux nombres de 2 bits
- Table de vérité
Entrées Sorties X1 X0 Y1 Y0 Z3 Z2 Z1 Z0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 0 0 1
Exercice 2 : Transcodeur binaire 7 segments
Si l'on vous demande de lire attentivement la première ligne de la table de vérité, c'est simplement pour vous faire constater qu'un zéro se fait en éteignant le segment 'g' et que donc pour éteindre un segment il faut lui mettre un 1 logique ce qui permet de déduire que pour allumer un segment il faut mettre un 0 logique.
- Table de vérité
Entrées Sorties sw3 sw2 sw1 sw0 g f e d c b a 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 0
Et voici le programme de correction :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY transcod7segs IS PORT(
sw : in std_logic_vector(3 downto 0);
s7segs : out std_logic_vector(6 downto 0));
END transcod7segs;
ARCHITECTURE arch of transcod7segs IS
BEGIN
with sw select
--gfedcba
s7segs <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
END;