Cours:TP M1102 TP 1 Corr

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M1102 : TP1 : solutions

Exercice 0

Avec deuxième fichier pour les contraintes

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;

entity exo0tp1 is port (
  e0,e1 : IN std_logic;
  s_et,s_ou : OUT std_logic);
END entity;

ARCHITECTURE behavior OF exo0tp1 IS
  SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
BEGIN
  s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
  s_et <= s_s(1);
  s_ou <= s_s(0);
  WITH s_e SELECT
    s_s <= "00" WHEN "00",
           "01" WHEN "01",
           "01" WHEN "10",
           "11" WHEN others;
END behavior;

et le fichier de contrainte :

To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
e0,Unknown,PIN_C10,7,B7_N0,PIN_C10,3.3-V LVTTL,,,,,
e1,Unknown,PIN_C11,7,B7_N0,PIN_C11,3.3-V LVTTL,,,,,
s_et,Unknown,PIN_A8,7,B7_N0,PIN_A8,3.3-V LVTTL,,,,,
s_ou,Unknown,PIN_A9,7,B7_N0,,3.3-V LVTTL,,,,,

Avec les contraintes dans le fichier VHDL

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;

entity exo0tp1 is port (
  e0,e1 : IN std_logic;
  s_et,s_ou : OUT std_logic);
END entity;

ARCHITECTURE behavior OF exo0tp1 IS
  SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
  attribute chip_pin : string;
  attribute chip_pin of e0 : signal is "c10";
  attribute chip_pin of e1 : signal is "c11";
  attribute chip_pin of s_et : signal is "a8";
  attribute chip_pin of s_ou : signal is "a9";
BEGIN
  s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
  s_et <= s_s(1);
  s_ou <= s_s(0);
  WITH s_e SELECT
    s_s <= "00" WHEN "00",
           "01" WHEN "01",
           "01" WHEN "10",
           "11" WHEN others;
END behavior;

Exercice 1

Table de vérité

Entrées			Sorties
e2	e1	e0	a	b	s
0	0	0	0	1	1
0	0	1	0	1	1
0	1	0	0	1	1
0	1	1	1	1	1
1	0	0	0	0	0
1	0	1	0	0	0
1	1	0	0	0	0
1	1	1	1	0	1