Cours:TP M1102 TP 1 Corr
Révision datée du 23 septembre 2020 à 16:00 par SergeMoutou (discussion | contributions) (→Exercice 0)
Sommaire
M1102 : TP1 : solutions
Exercice 0
Avec deuxième fichier pour les contraintes
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity exo0tp1 is port (
e0,e1 : IN std_logic;
s_et,s_ou : OUT std_logic);
END entity;
ARCHITECTURE behavior OF exo0tp1 IS
SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
BEGIN
s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
s_et <= s_s(1);
s_ou <= s_s(0);
WITH s_e SELECT
s_s <= "00" WHEN "00",
"01" WHEN "01",
"01" WHEN "10",
"11" WHEN others;
END behavior;
Avec les contraintes dans le fichier VHDL
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity exo0tp1 is port (
e0,e1 : IN std_logic;
s_et,s_ou : OUT std_logic);
END entity;
ARCHITECTURE behavior OF exo0tp1 IS
SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
attribute chip_pin : string;
attribute chip_pin of e0 : signal is "c10";
attribute chip_pin of e1 : signal is "c11";
attribute chip_pin of s_et : signal is "a8";
attribute chip_pin of s_ou : signal is "a9";
BEGIN
s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
s_et <= s_s(1);
s_ou <= s_s(0);
WITH s_e SELECT
s_s <= "00" WHEN "00",
"01" WHEN "01",
"01" WHEN "10",
"11" WHEN others;
END behavior;