Cours:TP M1102 TP 1 Corr : Différence entre versions
m |
m (→Exercice 0) |
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Ligne 2 : | Ligne 2 : | ||
=M1102 : TP1 : solutions= | =M1102 : TP1 : solutions= | ||
==Exercice 0== | ==Exercice 0== | ||
+ | ===Avec deuxième fichier pour les contraintes=== | ||
<source lang=VHDL> | <source lang=VHDL> | ||
library ieee; | library ieee; | ||
Ligne 15 : | Ligne 16 : | ||
ARCHITECTURE behavior OF exo0tp1 IS | ARCHITECTURE behavior OF exo0tp1 IS | ||
SIGNAL s_e,s_s: std_logic_vector(1 downto 0); | SIGNAL s_e,s_s: std_logic_vector(1 downto 0); | ||
+ | BEGIN | ||
+ | s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux | ||
+ | s_et <= s_s(1); | ||
+ | s_ou <= s_s(0); | ||
+ | WITH s_e SELECT | ||
+ | s_s <= "00" WHEN "00", | ||
+ | "01" WHEN "01", | ||
+ | "01" WHEN "10", | ||
+ | "11" WHEN others; | ||
+ | END behavior; | ||
+ | </source> | ||
+ | ===Avec les contraintes dans le fichier VHDL=== | ||
+ | <source lang=VHDL> | ||
+ | library ieee; | ||
+ | use ieee.std_logic_1164.all; | ||
+ | --use ieee.std_logic_arith.all; | ||
+ | --use ieee.std_logic_unsigned.all; | ||
+ | |||
+ | entity exo0tp1 is port ( | ||
+ | e0,e1 : IN std_logic; | ||
+ | s_et,s_ou : OUT std_logic); | ||
+ | END entity; | ||
+ | |||
+ | ARCHITECTURE behavior OF exo0tp1 IS | ||
+ | SIGNAL s_e,s_s: std_logic_vector(1 downto 0); | ||
+ | attribute chip_pin : string; | ||
+ | attribute chip_pin of e0 : signal is "c10"; | ||
+ | attribute chip_pin of e1 : signal is "c11"; | ||
+ | attribute chip_pin of s_et : signal is "a8"; | ||
+ | attribute chip_pin of s_ou : signal is "a9"; | ||
BEGIN | BEGIN | ||
s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux | s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux |
Version du 23 septembre 2020 à 16:00
Sommaire
M1102 : TP1 : solutions
Exercice 0
Avec deuxième fichier pour les contraintes
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity exo0tp1 is port (
e0,e1 : IN std_logic;
s_et,s_ou : OUT std_logic);
END entity;
ARCHITECTURE behavior OF exo0tp1 IS
SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
BEGIN
s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
s_et <= s_s(1);
s_ou <= s_s(0);
WITH s_e SELECT
s_s <= "00" WHEN "00",
"01" WHEN "01",
"01" WHEN "10",
"11" WHEN others;
END behavior;
Avec les contraintes dans le fichier VHDL
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity exo0tp1 is port (
e0,e1 : IN std_logic;
s_et,s_ou : OUT std_logic);
END entity;
ARCHITECTURE behavior OF exo0tp1 IS
SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
attribute chip_pin : string;
attribute chip_pin of e0 : signal is "c10";
attribute chip_pin of e1 : signal is "c11";
attribute chip_pin of s_et : signal is "a8";
attribute chip_pin of s_ou : signal is "a9";
BEGIN
s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
s_et <= s_s(1);
s_ou <= s_s(0);
WITH s_e SELECT
s_s <= "00" WHEN "00",
"01" WHEN "01",
"01" WHEN "10",
"11" WHEN others;
END behavior;