Cours:TP M1102 TP 1 Corr : Différence entre versions
(Page créée avec « <source lang=VHDL> =M1102 : TP1 : solutions= ==Exercice 0== library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all;... ») |
m |
||
| Ligne 1 : | Ligne 1 : | ||
| − | + | ||
=M1102 : TP1 : solutions= | =M1102 : TP1 : solutions= | ||
==Exercice 0== | ==Exercice 0== | ||
| − | + | <source lang=VHDL> | |
library ieee; | library ieee; | ||
use ieee.std_logic_1164.all; | use ieee.std_logic_1164.all; | ||
--use ieee.std_logic_arith.all; | --use ieee.std_logic_arith.all; | ||
--use ieee.std_logic_unsigned.all; | --use ieee.std_logic_unsigned.all; | ||
| + | |||
entity exo0tp1 is port ( | entity exo0tp1 is port ( | ||
e0,e1 : IN std_logic; | e0,e1 : IN std_logic; | ||
s_et,s_ou : OUT std_logic); | s_et,s_ou : OUT std_logic); | ||
END entity; | END entity; | ||
| + | |||
ARCHITECTURE behavior OF exo0tp1 IS | ARCHITECTURE behavior OF exo0tp1 IS | ||
SIGNAL s_e,s_s: std_logic_vector(1 downto 0); | SIGNAL s_e,s_s: std_logic_vector(1 downto 0); | ||
Version du 23 septembre 2020 à 15:56
M1102 : TP1 : solutions
Exercice 0
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity exo0tp1 is port (
e0,e1 : IN std_logic;
s_et,s_ou : OUT std_logic);
END entity;
ARCHITECTURE behavior OF exo0tp1 IS
SIGNAL s_e,s_s: std_logic_vector(1 downto 0);
BEGIN
s_e <= e1 & e0; -- A retenir : manière de regrouper des signaux
s_et <= s_s(1);
s_ou <= s_s(0);
WITH s_e SELECT
s_s <= "00" WHEN "00",
"01" WHEN "01",
"01" WHEN "10",
"11" WHEN others;
END behavior;
